lec networking

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# lec9 # lec9
This lecture has a corresponding activity found in `lab/` it is called `combinational-logic.md`.
It is more useful to practice combinational logic as opposed to read about it so the sub section here will be minimal in information.
It's recommended that you try as many of the problems in the activity until you understand the concept, _don't bother doing them all_.
## Combinational Logic
### OR
`a+b` is equivalent to saying `a` or `b`.
### AND
`ab` is equivalent to saying `a` and `b`.
Note that this syntax is simlar to multiplication so `a*b` is equivalent to the above.
### NOT
`!a` is equivalent to saying not `a`.
We can also denote it with a bar over the expression we want to _not_.
![Figure-Not](../img/not.png)
### Big AND
Behavior is the same as an `and` but instead of two inputs we can have many more inputs.
It will only ever return a 1 if all inputs are 1.
### Big OR
Again we are mimicing the behvior of the normal or gate but this time we can have multiple inputs as opposed to just two.
If only one of the many inputs is 1 then we return a 1 for the output of the Big OR.
## Decoders
Here we'll learn by doing
```
Selector = 2 Bits
Output = 4 Bits
```
As a challenge you can try using the combinational logic gates from above to try and tackle this yourself
|s1 |s2 |o3 |o2 |o1 |o0 |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 |
## Multiplexor
Typically we'll refer to multiplexors by their size.
> what does it do?
It takes a signal as `2^n` inputs and out puts out `n` signals as output.
Example: We have a selector(s0), two inputs[in0 & in1], and one output `out`.
The selector will select an input and we will generate some output in `out`.
|s0 | i0 | i1 | out|
|---|---|---|---|
|0 | 0 | 0 | 0|
|0 | 0 | 1 | 1|
|0 | 1 | 0 | 0|
|0 | 1 | 1 | 1|
|1 | 0 | 0 | 0|
|1 | 0 | 1 | 0|
|1 | 1 | 0 | 1|
|1 | 1 | 1 | 1|
This ultimately lets us pick data out of memory given some address. _Continuation of RDT_ + lec8
## Half Adder ## Pipelining
For now we'll take two inputs and get 1 output, with a carry-output. Instead of sending just one packet at a time we can send N packets across the network simultaneously.
We have two choices to deal with errors in this case however, `go-back-N` or `selective repeat`.
Let's add 2 bits ### Go-Back-N
ab |out THings we'll need to deal with:
00 |0
01 |1
10 |1
11 |0
What about the carry bit however? What would _it_ look like given the preivous operations? * timeout
* recevier acknowledgement
ab |carryout #### Sender
00 |0
01 |0
10 |0
11 |1
Before what this implies note that the result of the carryout resembles Sends N packets at a time and only re-sends according to highest value `ack` the receiver responds with.(_the next section explains this better_)
## Full Adder #### REceiver
We will respond with the _highest_ successful sequence number.
Say we were supposed to get 1 2 3 4 but 3 failed.
This is when we send ack1 ack2 but not `ack3 or 4`.
This tells the sender to resend everything from 3 onwards.
### Selective Repeat
Receiver gets `1 2 3 4` but `3` fails.
This time we send `ack1 ack2 nack3 ack4` and `3` is resent.
_This will take less bandwidth and still correct issues which can randomly happen._
If we imagine a window moving along a row of packet slots we only move that window along the row as the lowest(sequenced) packet is filled.
If a packet isn't `ack`d we wait for a timeout then we resend to the receiver.
Example: Say we send `1 2 3 4 5` but `3` is lost.
Our window would move from `1-5` to `2-7`, wait for timeout then resend, wait for `ack` then move forward as it receives `3`.
A useful link for visualizing selective repeat can found here:
Two inputs, One output, One carry-out, One carry-in
Here we'll add up `a & b`(inputs) and `c` carry-in
cab |output
000 |0
001 |1
010 |1
011 |0
100 |1
101 |0
110 |0
111 |1