csnotes/cst337/lec/lec11.md
2018-10-10 19:42:35 -07:00

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# lec11
_diagrams references implied for now_
Sequential Logic: at this point we effectively are dealing with state(_state machines_). Simply put we have _memory_ now.
## State Tables
In Q~s~ is our _Current state_ while Q~s+1~ is the next state
![](../img/lec11fig1.png)
| A | Q~s~ | Q~s+1~ |
|---|---|---|
| 0 | 0 | 0|
| 0 | 1 | 0|
| 1 | 0 | 0|
| 1 | 1 | 1|
We can try the same thing with an `or` gate:
![](../img/lec11fig2.png)
Keeping in mind that our effective input here is only `A`.
## Latches
Namely we are going to look at set-reset latches.
They should be able to do two things:
* store a state
* change state upon appropriately changed signals.
![](../img/lec11fig3.png)
Note that the above state machine the two rows show up as illogical; because both don't make sense in that context.
The actualy gate implementation of the above would look like the above.
![](../img/lec11fig4.png)
The same can also be done with `nor` gates making the whole operation much more efficient on transistor usage.
![](../img/lec11fig5.png)
## Clocking & Frequency
The period of the square wave in this case can be used to find the frequency.
We simple note that `1/T = F`.
This frequency is measured in cycles/second or _hertz_.
![](../img/lec11squareWave.png)
### Setup time & Hold time
Setup time would be some aount of time after the previous point where we wait for the combinational logic to perpetuate its results into memory.
A short period of time in the valley would be setup time
Hold time is the time that we wait before we start feeding input into our combinational logic(unit).
Say we wanted to start our combinational logic at the beginning of one of our plateaus.
## D Latches
_D stands for data_
![](../img/lec11dlatch.png)
Essentially we want to only read in D when the clock signal is high.
If it's low only we want to _block_ the signal from our output state.
The latch simply allows or disallows our input from passing through the other side based on what our clock is(high/low).
If D was 0 then it stays 0 when the clock goes low.
If D was 1 then it stays 1 when the clock goes low.
### Flip-Flop & Edge Triggering
Say we want to grab what ever D is but, only when we approach a falling edge.
The first latch opens as grabs any changes coming off D, then the the second opens just as the first closes.
We can reverse the two like in the next figure to acheive the opposite result: reading on the rising edge.