109 lines
4.0 KiB
Markdown
109 lines
4.0 KiB
Markdown
# lec11
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_diagrams references implied for now_
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Sequential Logic: at this point we effectively are dealing with state(_state machines_). Simply put we have _memory_ now.
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## State Tables
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In Q~s~ is our _Current state_ while Q~s+1~ is the next state
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| A | Q~s~ | Q~s+1~ |
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|---|---|---|
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| 0 | 0 | 0|
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| 0 | 1 | 0|
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| 1 | 0 | 0|
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| 1 | 1 | 1|
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We can try the same thing with an `or` gate:
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Keeping in mind that our effective input here is only `A`.
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## Latches
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Namely we are going to look at set-reset latches.
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They should be able to do two things:
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* store a state
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* change state upon appropriately changed signals.
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Note that the above state machine the two rows show up as illogical; because both don't make sense in that context.
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The actualy gate implementation of the above would look like the above.
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The same can also be done with `nor` gates making the whole operation much more efficient on transistor usage.
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The figure below is a more common implementation of a _Set-Reset Latch_.
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> Interesting but what is it used for?
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Setting a value or reseting a value to 0.
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That's all there is to it; either want to _set_ our ouput, or we want to reset it to zero.
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This is the first step in creating a device which can _actually_ store information to be used later on, in other words, memory!
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First we'll clean up our input: we are allowed to set _and_ reset which conceptually doesn't really make any sense since you should only be able to do one at a time.
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To stop this input from even being accepted we'll used _one_ input which splits into both `nor` gates [D].
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Next we want to decide _when_ to store the data because then we would even more control over our future _memory_.
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To do this we'll need some signal to dictate when we should pass our desdired data to our output(_which could be to a memory bank_).
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Our inputs now have `D` for the data we have now, and newly `C` for control(ling) if we want to store our data or not[1=yes 0=no].
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At this point this is what we call a _D-latch_
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### D Latches
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We saw earlier that we can now store data based on some control.
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Let's imagine that this control will regularly pulse between 0 and 1... similar to a _clock_.
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This means that if D wants to spas out of control we don't really care because we're going to allow `D`'s value through our controlled latch __only__ when `C` is high.
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This is all a _D-latch_ really is.
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It is just a mechanism to "read" a signal into some output signal _whenever we want to_.
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Even though the signals will keep flowing the output will be under our control, it just so happens that we are using a clock to control it out of convinience.
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## Clocking & Frequency
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The period of the square wave in this case can be used to find the frequency.
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We simple note that `1/T = F`.
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This frequency is measured in cycles/second or _hertz_.
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### Setup time & Hold time
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Setup time would be some aount of time after the previous point where we wait for the combinational logic to perpetuate its results into memory.
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A short period of time in the valley would be setup time
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Hold time is the time that we wait before we start feeding input into our combinational logic(unit).
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Say we wanted to start our combinational logic at the beginning of one of our plateaus.
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### Flip-Flop & Edge Triggering
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Referring back to the square wave let's say we want to grab the value of `D` when the control signal rises high, but _only_ when it rises.
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To do this we'll use the folowing structure:
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Grabbing the value of `D` when the clock signal falls low is just as easy however the answer will not be shown here.
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I suggest trying to find the answer yourself then looking up what such a logic diagram would look like.
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For pedantic sake here are the simplified diagrams of the above.
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_Only because they are so common._
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